senior digital design engineer.

The Senior Digital Design Engineer is designed to reward technical leadership, deep expertise, and end-product impact. You will receive:

• Attractive remuneration package.
• The opportunity to architect custom silicon that solves critical bandwidth and compute bottlenecks in modern AI infrastructure.
• Direct daily collaboration with elite silicon architects, verification leaders, and systems software engineers.

The Senior Digital Design Engineer will take complete end-to-end ownership of critical ASIC subsystems, driving design from early architectural definition through to tape-out and post-silicon validation. In this role, you will:

• Author specifications, evaluate and integrate complex IPs, and write high-performance, production-quality RTL in SystemVerilog/Verilog.
• Make micro-architectural decisions balancing Performance, Power, and Area (PPA) across compute clusters, custom accelerators, and memory subsystems.
• Author SDC constraints, run Static Timing Analysis (STA for setup/hold/OCV), and execute robust CDC/RDC analyses.
• Partner with Verification (UVM), Physical Design (floorplanning and CTS), Firmware, and System Validation teams to secure first-pass silicon.
• Build PrimeTime and Tcl automation scripts, debug simulation/emulation waveforms, and correlate pre- and post-silicon behavior across high-speed interfaces (PCIe, 400GE, UCIe).

The background for this Senior Digital Design Engineer role combines rigorous digital hardware design fundamentals with a proven track record in production ASIC delivery:

• 3+ years of hands-on experience in RTL design and front-end ASIC development, ideally with successful, full-cycle tape-outs.
• Deep, hands-on proficiency in SystemVerilog / Verilog and front-end EDA flows (Synthesis, Linting, STA, CDC/RDC analysis).
• Demonstrated experience configuring and integrating complex subsystems (e.g., PCIe, 100/400G Ethernet, UCIe, NoCs, multi-core clusters, or high-bandwidth memory).
• Strong command of multi-clock domain designs, asynchronous interfaces, and standard on-chip protocols (AMBA AXI, AHB, APB).
• he ability to translate architectural specifications into synthesis-friendly, maintainable hardware architectures designed for scale.
• Fluency in English

Hands-on experience in RTL design and front-end ASIC development, ideally with successful, full-c

If you have any questions regarding this Senior Digital Design Engineer position, you can contact Constantinos at 695 549 9060, from Monday to Friday between 10:00 and 16:00. Otherwise, feel free to contact me at ccapsiotis@randstad.gr.

We look forward to receiving your application, uploading your updated English CV by clicking the 'apply now' option.

Please note that for transparency and equity reasons, only those applications made online via our site will be assessed. After the screening of all the CVs received, we will only contact the candidates who meet the requirements of the job to arrange an interview. ​All applications are considered strictly confidential.